Integrated circuit memory devices are widely used in consumer and commercial electronics. Integrated circuit memory devices may also be integrated with logic circuits, microprocessors and/or other devices.
In general, high speed integrated circuit memory devices include a memory array 105, an input/output portion 101 and interface logic 103 as shown in FIG. 1. The input/output portion 101 receives commands or data via the external pins P1 through Pn and outputs internal data via the external pins P1 through Pn. The interface logic 103 receives commands from the input/output portion 101 and decodes the received commands to generate control signals C1 through Cn that control the memory array 105, and transmits the data via the input/output portion 101 to data lines RWD&lt;7:0&gt; of the memory array 105.
A direct access test mode is used to test memory cells in the memory array 105. The direct access test mode bypasses the interface logic 103 using a test apparatus and directly connects the external pins P1 through Pn to the control signals C1 through Cn of the memory array 105, to test the memory cells of the memory array 105. In the direct access test mode, data is written to memory cells, and then read back from the same memory cells. The data written to the memory cells is compared to the data read back, to thereby determine the condition (pass or fail) of the memory cells.
FIG. 2 is a block diagram of a high speed integrated circuit memory device 210 having a conventional direct access test mode. The integrated circuit memory device 210 includes a memory array 201, a controller 203 and a data output portion 205. Data is read back from the memory array 201 using external signals TestWRITE, TestRASB, TestCASB and the TestCLK in the direct access test mode.
FIG. 3 is a timing diagram of the data being read back from the high speed semiconductor memory device 210 of FIG. 2 in direct access test mode. When a row address strobe signal (TestRASB) transitions to "low" state, a corresponding word line (not shown) in the memory array 201 enables a test row address (RADDR) applied to address pins TestADDR&lt;11:0&gt;. When a TestCASB transitions to a "low" state, a column select line (CSL) in the memory array 201, transitions to a "high" state, corresponding to a test address (TestADDR&lt;11:0&gt;). When the TestWRITE signal transitions to a "low" state, a read operation begins. Accordingly, data read from the memory array 201 is transmitted to the data lines (RWD&lt;7:0&gt;).
The data transmitted to the data lines RWD&lt;7:0&gt; is stored in the data output portion 205 in response to the control signal TestReadLoad generated between first and second falling edges of the clock signal (TestCLK) applied to a clock pin. The data stored in the data output portion 205 is then output serially via an input/output pin (DQ) in response to the clock signal.
As described above, in conventional integrated circuit memory devices having a direct access test mode, an additional pin may be used to apply the clock signal to output data. As more pins are used for the direct access test mode, fewer IC memory devices can be tested simultaneously, thereby increasing the test time. Accordingly, there is a need to reduce the number of pins that need to be used in testing integrated circuit memory devices.